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authorPeter Maydell <peter.maydell@linaro.org>2021-05-10 20:08:39 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-05-25 16:01:43 +0100
commitb6889c5ae3895cf5a4322adb32b2133e9b91d158 (patch)
tree805365fadaeaade349c681f09aedca38cb36bcff /qga
parent382c7160d1cd9e815fb94d3889a5ddcf0e1845ab (diff)
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hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524
The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model it that way in hw/arm/armsse.c (along with the associated MPCs). We incorrectly also added an entry to the RAMInfo array for the AN524 in hw/arm/mps2-tz.c, which was pointless because the CPU would never see it. Delete it. The bug had no guest-visible effect because devices in the SSE-200 take priority over those in the board model (armsse.c maps s->board_memory at priority -2). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210510190844.17799-2-peter.maydell@linaro.org
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