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| author | Frank Chang <frank.chang@sifive.com> | 2022-09-09 21:42:08 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-27 11:23:57 +1000 |
| commit | a42bd0016654cafd6ca8ca4dbb82fc921ca19ae4 (patch) | |
| tree | 637dbc5da959eb928ac21a0b4a9445c6b16f9cc1 /qga | |
| parent | 9dfa6c2aec299fda9946c327e889087365a715b5 (diff) | |
| download | qemu-a42bd0016654cafd6ca8ca4dbb82fc921ca19ae4.zip qemu-a42bd0016654cafd6ca8ca4dbb82fc921ca19ae4.tar.gz qemu-a42bd0016654cafd6ca8ca4dbb82fc921ca19ae4.tar.bz2 | |
target/riscv: debug: Determine the trigger type from tdata1.type
Current RISC-V debug assumes that only type 2 trigger is supported.
To allow more types of triggers to be supported in the future
(e.g. type 6 trigger, which is similar to type 2 trigger with additional
functionality), we should determine the trigger type from tdata1.type.
RV_MAX_TRIGGERS is also introduced in replacement of TRIGGER_TYPE2_NUM.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
[bmeng: fixed MXL_RV128 case, and moved macros to the following patch]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220909134215.1843865-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'qga')
0 files changed, 0 insertions, 0 deletions