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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:14 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-10-24 12:19:14 +0100 |
| commit | 23adb8618caf24ab7cbb41fb2f27bad1c429cbda (patch) | |
| tree | f4cac950e22e7d629ec7c7b07ff93dfa41777fd2 /qga | |
| parent | 0e7b176ae01d5a664d4cbf619a7315819494e6cb (diff) | |
| download | qemu-23adb8618caf24ab7cbb41fb2f27bad1c429cbda.zip qemu-23adb8618caf24ab7cbb41fb2f27bad1c429cbda.tar.gz qemu-23adb8618caf24ab7cbb41fb2f27bad1c429cbda.tar.bz2 | |
target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0
The ARM ARM requires that the FPINST and FPINST2 VFP control
registers are not accessible to code at EL0. We were already
correctly implementing this for reads of these registers; add
the missing check for the write code path.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 1412967447-20931-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'qga')
0 files changed, 0 insertions, 0 deletions