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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-11 16:39:45 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-13 15:14:04 +0100 |
| commit | fa288de272c5c8a66d5eb683b123706a52bc7ad6 (patch) | |
| tree | 1e618f040e9883f78901f24990b451274d120a1e /qga/main.c | |
| parent | 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 (diff) | |
| download | qemu-fa288de272c5c8a66d5eb683b123706a52bc7ad6.zip qemu-fa288de272c5c8a66d5eb683b123706a52bc7ad6.tar.gz qemu-fa288de272c5c8a66d5eb683b123706a52bc7ad6.tar.bz2 | |
target/arm: Convert the VFP load/store multiple insns to decodetree
Convert the VFP load/store multiple insns to decodetree.
This includes tightening up the UNDEF checking for pre-VFPv3
CPUs which only have D0-D15 : they now UNDEF for any access
to D16-D31, not merely when the smallest register in the
transfer list is in D16-D31.
This conversion does not try to share code between the single
precision and the double precision versions; this looks a bit
duplicative of code, but it leaves the door open for a future
refactoring which gets rid of the use of the "F0" registers
by inlining the various functions like gen_vfp_ld() and
gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }"
conditionalisation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'qga/main.c')
0 files changed, 0 insertions, 0 deletions