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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:39:02 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | c696e1f2b392af19653e82da26df3c61b85ab5a2 (patch) | |
| tree | 1fd7a96bbc40a5bf5aae06f7de551b684876c443 /qemu-seccomp.c | |
| parent | 8f2ac39d5d307589faca1d00d55a1a8054d53b0e (diff) | |
| download | qemu-c696e1f2b392af19653e82da26df3c61b85ab5a2.zip qemu-c696e1f2b392af19653e82da26df3c61b85ab5a2.tar.gz qemu-c696e1f2b392af19653e82da26df3c61b85ab5a2.tar.bz2 | |
hw/sd: Add Cadence SDHCI emulation
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'qemu-seccomp.c')
0 files changed, 0 insertions, 0 deletions