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| author | Alexei Filippov <alexei.filippov@syntacore.com> | 2024-05-03 13:30:52 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-06-03 11:12:12 +1000 |
| commit | 6c9a344247132ac6c3d0eb9670db45149a29c88f (patch) | |
| tree | d328462b1e3591db08168deff802b6d2263d1657 /qemu-keymap.c | |
| parent | 68e7c86927afa240fa450578cb3a4f18926153e4 (diff) | |
| download | qemu-6c9a344247132ac6c3d0eb9670db45149a29c88f.zip qemu-6c9a344247132ac6c3d0eb9670db45149a29c88f.tar.gz qemu-6c9a344247132ac6c3d0eb9670db45149a29c88f.tar.bz2 | |
target/riscv: do not set mtval2 for non guest-page faults
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.
In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*
Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'qemu-keymap.c')
0 files changed, 0 insertions, 0 deletions