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author | Peter Maydell <peter.maydell@linaro.org> | 2020-02-14 17:51:13 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:02 +0000 |
commit | 10054016eda1b13bdd8340d100fd029cc8b58f36 (patch) | |
tree | f0e32b6910abe1c2c4c2354890855b29b5fd8a7a /qemu-io-cmds.c | |
parent | 62d96ff48510f4bf648ad12f5d3a5507227b026f (diff) | |
download | qemu-10054016eda1b13bdd8340d100fd029cc8b58f36.zip qemu-10054016eda1b13bdd8340d100fd029cc8b58f36.tar.gz qemu-10054016eda1b13bdd8340d100fd029cc8b58f36.tar.bz2 |
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.
Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struct; we
choose to move all the ID_MMFRn registers for consistency.
Fixes: 3d6ad6bb466f
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-19-peter.maydell@linaro.org
Diffstat (limited to 'qemu-io-cmds.c')
0 files changed, 0 insertions, 0 deletions