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author | Peter Maydell <peter.maydell@linaro.org> | 2022-01-21 10:31:25 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2022-01-21 10:31:25 +0000 |
commit | 5e9d14f2bea6df89c0675df953f9c839560d2266 (patch) | |
tree | 4cfbf3189ca73a5e5372f3b032a3d4cbcb59dd1f /qemu-img-cmds.hx | |
parent | 2c89b5af5e72ab8c9d544c6e30399528b2238827 (diff) | |
parent | f297245f6a780f496fb171af6fcd21ff3e6783c3 (diff) | |
download | qemu-5e9d14f2bea6df89c0675df953f9c839560d2266.zip qemu-5e9d14f2bea6df89c0675df953f9c839560d2266.tar.gz qemu-5e9d14f2bea6df89c0675df953f9c839560d2266.tar.bz2 |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220121-1' into staging
Third RISC-V PR for QEMU 7.0
* Fixes for OpenTitan timer
* Correction of OpenTitan PLIC stride length
* RISC-V KVM support
* Device tree code cleanup
* Support for the Zve64f and Zve32f extensions
* OpenSBI binary loading support for the Spike machine
* Removal of OpenSBI ELFs
* Support for the UXL field in xstatus
# gpg: Signature made Fri 21 Jan 2022 05:57:09 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20220121-1: (61 commits)
target/riscv: Relax UXL field for debugging
target/riscv: Enable uxl field write
target/riscv: Set default XLEN for hypervisor
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Adjust vector address with mask
target/riscv: Fix check range for first fault only
target/riscv: Remove VILL field in VTYPE
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Split out the vill from vtype
target/riscv: Split pm_enabled into mask and base
target/riscv: Calculate address according to XLEN
target/riscv: Alloc tcg global for cur_pm[mask|base]
target/riscv: Create current pm fields in env
target/riscv: Adjust csr write mask with XLEN
target/riscv: Relax debug check for pm write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Extend pc for runtime pc write
target/riscv: Ignore the pc bits above XLEN
target/riscv: Create xl field in env
target/riscv: Sign extend pc for different XLEN
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'qemu-img-cmds.hx')
0 files changed, 0 insertions, 0 deletions