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authorScott Wood <scottwood@freescale.com>2012-12-21 16:15:39 +0000
committerAlexander Graf <agraf@suse.de>2013-01-07 17:37:09 +0100
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openpic: lower interrupt when reading the MSI register
This will stop things from breaking once it's properly treated as a level-triggered interrupt. Note that it's the MPIC's MSI cascade interrupts that are level-triggered; the individual MSIs are edge-triggered. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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