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authorRichard Henderson <richard.henderson@linaro.org>2024-05-24 16:20:16 -0700
committerPeter Maydell <peter.maydell@linaro.org>2024-05-28 14:23:52 +0100
commitdb36e14501e8745a6e23f611f917d40a27cc5dee (patch)
tree889a316468dfe6e6ee63a15760e92cad3e8008eb /qapi
parent2fda0e776ae5360910f3521ec2608b535f338d90 (diff)
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target/arm: Use PLD, PLDW, PLI not NOP for t32
This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2, but are introduced with ARMv7 and ARMv7MP respectively. For clarity, do not use NOP for PLD. Note that there is no PLDW (literal). Architecturally in the T1 encoding of "PLD (literal)" bit 5 is "(0)", which means that it should be zero and if it is not then the behaviour is CONSTRAINED UNPREDICTABLE (might UNDEF, NOP, or ignore the value of the bit). In our implementation we have patterns for both: + PLD 1111 1000 -001 1111 1111 ------------ # (literal) + PLD 1111 1000 -011 1111 1111 ------------ # (literal) and so we effectively ignore the value of bit 5. (This is a permitted option for this CONSTRAINED UNPREDICTABLE.) This isn't a behaviour change in this commit, since we previously had NOP lines for both those patterns. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240524232121.284515-3-richard.henderson@linaro.org [PMM: adjusted commit message to note that PLD (lit) T1 bit 5 being 1 is an UNPREDICTABLE case.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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