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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-05-15 16:09:52 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-05-25 23:39:11 +0200 |
| commit | a3e7f6d05d8bf38b0337fabc438d32c46948ccff (patch) | |
| tree | 1092edd495afe4073481022112ddb0605eaf2187 /python | |
| parent | 33627ab237168fa624435eb8ae87f82a2ba9d7f5 (diff) | |
| download | qemu-a3e7f6d05d8bf38b0337fabc438d32c46948ccff.zip qemu-a3e7f6d05d8bf38b0337fabc438d32c46948ccff.tar.gz qemu-a3e7f6d05d8bf38b0337fabc438d32c46948ccff.tar.bz2 | |
test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
The digest_addr is set to "src_addr + 0x1000000", where src_addr is the DRAM
base address. However, the value 0x1000000 (16MB) is too large because the
AST1030 does not support DRAM, and its SRAM size is only 768KB.
A range size of 0x10000 (64KB) is sufficient for HACE test cases, as the test
vector size does not exceed 64KB.
Updates:
1. Direct Access Mode
Update digest_addr to "src_addr + 0x10000" in the following functions:
aspeed_test_md5
aspeed_test_sha256
aspeed_test_sha512
2. Scatter-Gather (SG) Mode
Update source address for different SG buffer addresses in the following
functions:
src_addr1 = src_addr + 0x10000
src_addr2 = src_addr + 0x20000
src_addr3 = src_addr + 0x30000
digest_addr = src_addr + 0x40000
aspeed_test_sha256_sg
aspeed_test_sha512_sg
3. ACC Mode Update
Update the SG List start address: src_addr + 0x10000
Update the SG List buffer size to 0x30000 (192KB).
buffer_addr = src_addr + 0x10000
digest_addr = src_addr + 0x40000
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Fabiano Rosas <farosas@suse.de>
Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-21-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions