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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-29 18:08:19 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-06-24 16:45:41 +0200 |
| commit | a071578b93e850dcbebbe2c0cfe86e7977ddffa7 (patch) | |
| tree | e2625a07a7bf6349e793969cf059d5685104eb8c /python | |
| parent | 6eb223104c4e5cdfeaf57cff20fb1ad54084393b (diff) | |
| download | qemu-a071578b93e850dcbebbe2c0cfe86e7977ddffa7.zip qemu-a071578b93e850dcbebbe2c0cfe86e7977ddffa7.tar.gz qemu-a071578b93e850dcbebbe2c0cfe86e7977ddffa7.tar.bz2 | |
target/mips: Raise exception when DINSV opcode used with DSP disabled
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
If the Module/ASE is not implemented, executing such an instruction
must cause a Reserved Instruction Exception.
The DINSV instruction lists the following exceptions:
- Reserved Instruction
- DSP Disabled
If the MIPS core doesn't support the DSP module, or the DSP is
disabled, do not handle the '$rt = $0' case as a no-op but raise
the proper exception instead.
Cc: Jia Liu <proljc@gmail.com>
Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210529165443.1114402-1-f4bug@amsat.org>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions