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| author | Cédric Le Goater <clg@kaod.org> | 2021-10-12 08:20:07 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2021-10-12 08:20:07 +0200 |
| commit | 45a904af3861b5457050e55271e1386a7040f04f (patch) | |
| tree | e39eefd28904c6e9b1e905478b4bb5950b627d29 /python | |
| parent | c09124dcb8401a0d635b4a52b295e9b3fc12392a (diff) | |
| download | qemu-45a904af3861b5457050e55271e1386a7040f04f.zip qemu-45a904af3861b5457050e55271e1386a7040f04f.tar.gz qemu-45a904af3861b5457050e55271e1386a7040f04f.tar.bz2 | |
aspeed/smc: Add watchdog Control/Status Registers
The Aspeed SoCs have a dual boot function for firmware fail-over
recovery. The system auto-reboots from the second flash if the main
flash does not boot successfully within a certain amount of time. This
function is called alternate boot (ABR) in the FMC controllers.
On AST2400/AST2500, ABR is enabled by hardware strapping in SCU70 to
enable the 2nd watchdog timer, on AST2600, through register SCU510.
If the boot on the the main flash succeeds, the firmware should
disable the 2nd watchdog timer. If not, the BMC is reset and the CE0
and CE1 mappings are swapped to restart the BMC from the 2nd flash.
On the AST2600, the ABR registers controlling the 2nd watchdog timer
were moved from the watchdog register to the FMC controller and the
FMC model should be able to control WDT2 through its own register set.
This requires more work. For now, add dummy read/write handlers to let
the FW disable the 2nd watchdog without error.
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Reported-by: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions