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author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2025-04-29 09:44:16 -0300 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2025-05-19 13:41:44 +1000 |
commit | 11766e17616a5a4181d4a63f88adf67ac52c553b (patch) | |
tree | 46518270012168ca1d1d3b2ec5e00543713d4f0d /python | |
parent | b6096103494506514d9bfa442f62fef36ffc8fba (diff) | |
download | qemu-11766e17616a5a4181d4a63f88adf67ac52c553b.zip qemu-11766e17616a5a4181d4a63f88adf67ac52c553b.tar.gz qemu-11766e17616a5a4181d4a63f88adf67ac52c553b.tar.bz2 |
target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
We need the reg_id_ulong() helper to be a macro to be able to create a
static array of KVMCPUConfig that will hold CSR information.
Despite the amount of changes all of them are tedious/trivial:
- replace instances of "kvm_riscv_reg_id_ulong" with
"KVM_RISCV_REG_ID_ULONG";
- RISCV_CORE_REG(), RISCV_CSR_REG(), RISCV_CONFIG_REG() and
RISCV_VECTOR_CSR_REG() only receives one 'name' arg. Remove unneeded
'env' variables when applicable.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250429124421.223883-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions