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| author | Deepak Gupta <debug@rivosinc.com> | 2025-03-05 22:46:36 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-19 16:34:32 +1000 |
| commit | d2c5759c8dd4c00195d4ebecc7d009e41df6baef (patch) | |
| tree | d7800db6218c2f4578582a0a720118dab9778393 /python/qemu/utils/qemu_ga_client.py | |
| parent | 86c78b280607fcff787866a03374047c65037a90 (diff) | |
| download | qemu-d2c5759c8dd4c00195d4ebecc7d009e41df6baef.zip qemu-d2c5759c8dd4c00195d4ebecc7d009e41df6baef.tar.gz qemu-d2c5759c8dd4c00195d4ebecc7d009e41df6baef.tar.bz2 | |
target/riscv: fixes a bug against `ssamoswap` behavior in M-mode
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a zimop like other shadow stack instructions).
If shadow stack is not enabled (via xenvcfg.SSE) and effective priv is
less than M then `ssamoswap` must result in an illegal instruction
exception. However if effective priv is M, then `ssamoswap` results in
store/AMO access fault. See Section "22.2.3. Shadow Stack Memory
Protection" of priv spec.
Fixes: f06bfe3dc38c ("target/riscv: implement zicfiss instructions")
Reported-by: Ved Shanbhogue <ved@rivosinc.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250306064636.452396-2-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'python/qemu/utils/qemu_ga_client.py')
0 files changed, 0 insertions, 0 deletions