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authorMatheus Tavares Bernardino <quic_mathbern@quicinc.com>2024-05-20 12:53:04 -0300
committerBrian Cain <bcain@quicinc.com>2024-06-08 17:48:50 -0700
commita1852002c7509569eaaedb783925f34350fe0a84 (patch)
treea7112e5376213556df5e9d425a11180dd75d88fa /net
parent3e246da2c3f85298b52f8a1154b832acf36aa656 (diff)
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Hexagon: fix HVX store new
At 09a7e7db0f (Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc, 2024-03-06), we've changed the logic of check_new_value() to use the new pre-calculated packet->insn[...].dest_idx instead of calculating the index on the fly using opcode_reginfo[...]. The dest_idx index is calculated roughly like the following: for reg in iset[tag]["syntax"]: if reg.is_written(): dest_idx = regno break Thus, we take the first register that is writtable. Before that, however, we also used to follow an alphabetical order on the register type: 'd', 'e', 'x', and 'y'. No longer following that makes us select the wrong register index and the HVX store new instruction does not update the memory like expected. Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com> Message-Id: <f548dc1c240819c724245e887f29f918441e9125.1716220379.git.quic_mathbern@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com>
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