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| author | Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> | 2020-11-30 17:01:17 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-12-17 21:56:43 -0800 |
| commit | 529577457cbba9e429af629c46204f63e50fa832 (patch) | |
| tree | 0b64abe8cb934d740a544d8ae3735d6c17a1b950 /net | |
| parent | c63ca4ff7f81116c26984973052991ff0bd7caec (diff) | |
| download | qemu-529577457cbba9e429af629c46204f63e50fa832.zip qemu-529577457cbba9e429af629c46204f63e50fa832.tar.gz qemu-529577457cbba9e429af629c46204f63e50fa832.tar.bz2 | |
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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0 files changed, 0 insertions, 0 deletions