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| author | TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> | 2024-10-07 10:56:54 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-10-22 11:57:25 -0700 |
| commit | a31768c0192a6f1f62d07c4985a77814be34a915 (patch) | |
| tree | 5924736e027687c72db5521dda3df2e85963e5c6 /module-common.c | |
| parent | 5a63f5998791460342ddc1fcd74db5909d00a2b9 (diff) | |
| download | qemu-a31768c0192a6f1f62d07c4985a77814be34a915.zip qemu-a31768c0192a6f1f62d07c4985a77814be34a915.tar.gz qemu-a31768c0192a6f1f62d07c4985a77814be34a915.tar.bz2 | |
tcg/riscv: Implement vector cmp/cmpsel ops
Extend comparison results from mask registers to SEW-width elements,
following recommendations in The RISC-V SPEC Volume I (Version 20240411).
This aligns with TCG's cmp_vec behavior by expanding compare results to
full element width: all 1s for true, all 0s for false.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241007025700.47259-7-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'module-common.c')
0 files changed, 0 insertions, 0 deletions