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authorPeter Maydell <peter.maydell@linaro.org>2019-01-09 16:08:31 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-01-09 16:08:31 +0000
commit8ae951fbc1068308313b2c57a4fc3c68451641f4 (patch)
tree0e6011b3ec47674859cd12a6e77ae8a8387f70a8 /linux-user
parent147923b1a901a0370f83a0f4c58ec1baffef22f0 (diff)
parent3a8eb78e6c135422017888380db091793039b6dd (diff)
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190109' into staging
ppc patch queue 2019-01-09 Second main pull request for qemu-4.0. Highlights are: * Final parts of XIVE support for pseries (without KVM) * Preliminary work for PHB hotplug * Starting to use TCG vector operations This includes some changes in the PCI core, which Michael Tsirkin requested come through this tree, since they're primarily of interest for ppc. # gpg: Signature made Tue 08 Jan 2019 22:44:10 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.0-20190109: (29 commits) spapr: enable XIVE MMIOs at reset spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS ppc/xics: allow ICSState to have an offset 0 spapr: move the qemu_irq array under the machine pnv/psi: move the ICSState qemu_irq array under the PSI device model ppc: export the XICS and XIVE set_irq handlers spapr: return from post_load method when RTC import fails ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPU ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU spapr: modify the prototype of the cpu_intc_create() method spapr/xive: simplify the sPAPR IRQ qirq method for XIVE spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h pci: allow cleanup/unregistration of PCI root buses spapr: move spapr_create_phb() to core machine code MAINTAINERS: add qemu_vga.ndrv file entry for Mac machines MAINTAINERS: Add some missing ppc-related files target/ppc: replace AVR* macros with Vsr* macros target/ppc: move FP and VMX registers into aligned vsr register array target/ppc: merge ppc_vsr_t and ppc_avr_t union types target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user')
-rw-r--r--linux-user/ppc/signal.c28
1 files changed, 16 insertions, 12 deletions
diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c
index 2ae120a..619a569 100644
--- a/linux-user/ppc/signal.c
+++ b/linux-user/ppc/signal.c
@@ -258,8 +258,8 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
/* Save Altivec registers if necessary. */
if (env->insns_flags & PPC_ALTIVEC) {
uint32_t *vrsave;
- for (i = 0; i < ARRAY_SIZE(env->avr); i++) {
- ppc_avr_t *avr = &env->avr[i];
+ for (i = 0; i < 32; i++) {
+ ppc_avr_t *avr = cpu_avr_ptr(env, i);
ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i];
__put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
@@ -281,15 +281,17 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
/* Save VSX second halves */
if (env->insns_flags2 & PPC2_VSX) {
uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
- for (i = 0; i < ARRAY_SIZE(env->vsr); i++) {
- __put_user(env->vsr[i], &vsregs[i]);
+ for (i = 0; i < 32; i++) {
+ uint64_t *vsrl = cpu_vsrl_ptr(env, i);
+ __put_user(*vsrl, &vsregs[i]);
}
}
/* Save floating point registers. */
if (env->insns_flags & PPC_FLOAT) {
- for (i = 0; i < ARRAY_SIZE(env->fpr); i++) {
- __put_user(env->fpr[i], &frame->mc_fregs[i]);
+ for (i = 0; i < 32; i++) {
+ uint64_t *fpr = cpu_fpr_ptr(env, i);
+ __put_user(*fpr, &frame->mc_fregs[i]);
}
__put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]);
}
@@ -373,8 +375,8 @@ static void restore_user_regs(CPUPPCState *env,
#else
v_regs = (ppc_avr_t *)frame->mc_vregs.altivec;
#endif
- for (i = 0; i < ARRAY_SIZE(env->avr); i++) {
- ppc_avr_t *avr = &env->avr[i];
+ for (i = 0; i < 32; i++) {
+ ppc_avr_t *avr = cpu_avr_ptr(env, i);
ppc_avr_t *vreg = &v_regs[i];
__get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
@@ -393,16 +395,18 @@ static void restore_user_regs(CPUPPCState *env,
/* Restore VSX second halves */
if (env->insns_flags2 & PPC2_VSX) {
uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
- for (i = 0; i < ARRAY_SIZE(env->vsr); i++) {
- __get_user(env->vsr[i], &vsregs[i]);
+ for (i = 0; i < 32; i++) {
+ uint64_t *vsrl = cpu_vsrl_ptr(env, i);
+ __get_user(*vsrl, &vsregs[i]);
}
}
/* Restore floating point registers. */
if (env->insns_flags & PPC_FLOAT) {
uint64_t fpscr;
- for (i = 0; i < ARRAY_SIZE(env->fpr); i++) {
- __get_user(env->fpr[i], &frame->mc_fregs[i]);
+ for (i = 0; i < 32; i++) {
+ uint64_t *fpr = cpu_fpr_ptr(env, i);
+ __get_user(*fpr, &frame->mc_fregs[i]);
}
__get_user(fpscr, &frame->mc_fregs[32]);
env->fpscr = (uint32_t) fpscr;