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| author | Bin Meng <bin.meng@windriver.com> | 2020-10-28 13:30:02 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | 3400b15bbe0fbc672fee9a18268154b07a1fed2e (patch) | |
| tree | 8481d450f42487041164e70c0181c33983c0a1e7 /libdecnumber | |
| parent | 08b86e3b8f5209b1c39f22a6d367f347eaf0f8be (diff) | |
| download | qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.zip qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.tar.gz qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.tar.bz2 | |
hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
called SGMII PHY module and the CFG module, as documented in the
chipset datasheet.
This creates a single file that groups these 2 modules, providing
the minimum functionalities that make the HSS DDR initialization
codes happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'libdecnumber')
0 files changed, 0 insertions, 0 deletions