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author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-11 11:17:31 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-11 11:17:31 +0000 |
commit | 2f027fc52d4b444a47cb05a9c96697372a6b57d2 (patch) | |
tree | fd7d45998124be4a5e4cbecdf146a46ab308defc /libdecnumber/dpd | |
parent | 3f208fd76bcc91a8506681bb8472f2398fe6f487 (diff) | |
download | qemu-2f027fc52d4b444a47cb05a9c96697372a6b57d2.zip qemu-2f027fc52d4b444a47cb05a9c96697372a6b57d2.tar.gz qemu-2f027fc52d4b444a47cb05a9c96697372a6b57d2.tar.bz2 |
target-arm: Implement NSACR trapping behaviour
Implement some corner cases of the behaviour of the NSACR
register on ARMv8:
* if EL3 is AArch64 then accessing the NSACR from Secure EL1
with AArch32 should trap to EL3
* if EL3 is not present or is AArch64 then reads from NS EL1 and
NS EL2 return constant 0xc00
It would in theory be possible to implement all these with
a single reginfo definition, but for clarity we use three
separate definitions for the three cases and install the
right one based on the CPU feature flags.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1454506721-11843-7-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'libdecnumber/dpd')
0 files changed, 0 insertions, 0 deletions