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authorPhilipp Tomsich <philipp.tomsich@vrull.eu>2022-02-02 01:52:45 +0100
committerAlistair Francis <alistair.francis@wdc.com>2022-02-16 12:24:18 +1000
commit79bf3b51acb4a6245b500005859e8b1d1611302f (patch)
tree2869f86c4d05e849ff7a2d2090de04ad2f5350aa /iothread.c
parent3b91323e33d85150eb482458b1f1e2b08a59d8a2 (diff)
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target/riscv: access configuration through cfg_ptr in DisasContext
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow copies (in DisasContext) of some of the elements available in the RISCVCPUConfig structure. This commit redirects accesses to use the cfg_ptr copied into DisasContext and removes the shallow copies. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu> [ Changes by AF: - Fixup checkpatch failures ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'iothread.c')
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