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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-01-21 12:49:48 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-01-21 12:49:48 +0000 |
| commit | bbca106776ab5decb01a0f101c67524546a1fcd2 (patch) | |
| tree | 13172c120de4d581c202c7717aee2a1a160547f1 /include | |
| parent | f12313995c5bc241515fd3c4c6f61859584b0086 (diff) | |
| parent | 0d4bfd7df809863b1f45fad35229fb9419527d06 (diff) | |
| download | qemu-bbca106776ab5decb01a0f101c67524546a1fcd2.zip qemu-bbca106776ab5decb01a0f101c67524546a1fcd2.tar.gz qemu-bbca106776ab5decb01a0f101c67524546a1fcd2.tar.bz2 | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190121' into staging
target-arm queue:
* hw/char/stm32f2xx_usart: Do not update data register when device is disabled
* hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
* target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
* ftgmac100: implement the new MDIO interface on Aspeed SoC
* implement the ARMv8.3-PAuth extension
* improve emulation of the ARM PMU
# gpg: Signature made Mon 21 Jan 2019 10:42:11 GMT
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190121: (48 commits)
target/arm: Implement PMSWINC
target/arm: PMU: Set PMCR.N to 4
target/arm: PMU: Add instruction and cycle events
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
target/arm: Define FIELDs for ID_DFR0
target/arm: Implement PMOVSSET
target/arm: Allow AArch32 access for PMCCFILTR
target/arm: Filter cycle counter based on PMCCFILTR_EL0
target/arm: Swap PMU values before/after migrations
target/arm: Reorganize PMCCNTR accesses
migration: Add post_save function to VMStateDescription
target/arm: Tidy TBI handling in gen_a64_set_pc
target/arm: Enable PAuth for user-only
target/arm: Enable PAuth for -cpu max
target/arm: Add PAuth system registers
target/arm: Implement pauth_computepac
target/arm: Implement pauth_addpac
target/arm: Implement pauth_auth
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/acpi/acpi-defs.h | 2 | ||||
| -rw-r--r-- | include/migration/vmstate.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 4ed160a..f9aa4bd 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -626,6 +626,8 @@ struct AcpiIortItsGroup { } QEMU_PACKED; typedef struct AcpiIortItsGroup AcpiIortItsGroup; +#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1 + struct AcpiIortSmmu3 { ACPI_IORT_NODE_HEADER_DEF uint64_t base_address; diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 61bef3e..067b126 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -185,6 +185,7 @@ struct VMStateDescription { int (*pre_load)(void *opaque); int (*post_load)(void *opaque, int version_id); int (*pre_save)(void *opaque); + int (*post_save)(void *opaque); bool (*needed)(void *opaque); const VMStateField *fields; const VMStateDescription **subsections; |