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authorJoel Stanley <joel@jms.id.au>2021-05-01 10:03:51 +0200
committerCédric Le Goater <clg@kaod.org>2021-05-01 10:03:51 +0200
commita3888d757acdd92c4c49fb9cad5f5733d8280a86 (patch)
treea458b8ac08971a908bc0991d19fd5349d2f00336 /include
parentc5475b3f9aa28c1c1422c7de0bab40c5dff77341 (diff)
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aspeed: Integrate HACE
Add the hash and crypto engine model to the Aspeed socs. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210409000253.1475587-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include')
-rw-r--r--include/hw/arm/aspeed_soc.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 9359d6d..d9161d2 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -21,6 +21,7 @@
#include "hw/rtc/aspeed_rtc.h"
#include "hw/i2c/aspeed_i2c.h"
#include "hw/ssi/aspeed_smc.h"
+#include "hw/misc/aspeed_hace.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
@@ -50,6 +51,7 @@ struct AspeedSoCState {
AspeedTimerCtrlState timerctrl;
AspeedI2CState i2c;
AspeedSCUState scu;
+ AspeedHACEState hace;
AspeedXDMAState xdma;
AspeedSMCState fmc;
AspeedSMCState spi[ASPEED_SPIS_NUM];
@@ -133,6 +135,7 @@ enum {
ASPEED_DEV_XDMA,
ASPEED_DEV_EMMC,
ASPEED_DEV_KCS,
+ ASPEED_DEV_HACE,
};
#endif /* ASPEED_SOC_H */