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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-07-06 17:32:09 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-07-06 17:32:09 +0100 |
| commit | 91d35509903464c7f4b9ed56be223d7370d3597c (patch) | |
| tree | fc3fcd649d12a9afee5ce5cd9843e04dd5c008d8 /include | |
| parent | 0c56c6ab68902281094c7aac6305e2321c34c187 (diff) | |
| parent | 1f00b27f17518a1bcb4cedca49eaec96a4d560bd (diff) | |
| download | qemu-91d35509903464c7f4b9ed56be223d7370d3597c.zip qemu-91d35509903464c7f4b9ed56be223d7370d3597c.tar.gz qemu-91d35509903464c7f4b9ed56be223d7370d3597c.tar.bz2 | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20160706' into staging
misc updates
# gpg: Signature made Wed 06 Jul 2016 17:17:02 BST
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-tcg-20160706:
tcg: Improve the alignment check infrastructure
tcg: Optimize spills of constants
tcg: Fix name for high-half register
build: Use $(CCAS) for compiling .S files
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/exec/cpu-all.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6a6796d..b6a7059 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -288,14 +288,22 @@ CPUArchState *cpu_copy(CPUArchState *env); #if !defined(CONFIG_USER_ONLY) /* Flags stored in the low bits of the TLB virtual address. These are - defined so that fast path ram access is all zeros. */ + * defined so that fast path ram access is all zeros. + * The flags all must be between TARGET_PAGE_BITS and + * maximum address alignment bit. + */ /* Zero if TLB entry is valid. */ -#define TLB_INVALID_MASK (1 << 3) +#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1)) /* Set if TLB entry references a clean RAM page. The iotlb entry will contain the page physical address. */ -#define TLB_NOTDIRTY (1 << 4) +#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) /* Set if TLB entry is an IO callback. */ -#define TLB_MMIO (1 << 5) +#define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) + +/* Use this mask to check interception with an alignment mask + * in a TCG backend. + */ +#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); |