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author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 13:12:37 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 13:12:37 -0700 |
commit | 88d5814e6b02515f823086abb91dc7cdbb31c9f1 (patch) | |
tree | dcce7c9d3f084a14aca85dcef4feb65ff63a48a3 /include | |
parent | eab18e4021b80a03729424385c506e2454cd635c (diff) | |
parent | 7f176c5a0bcb70492f3b158a36311e75f1eb87d7 (diff) | |
download | qemu-88d5814e6b02515f823086abb91dc7cdbb31c9f1.zip qemu-88d5814e6b02515f823086abb91dc7cdbb31c9f1.tar.gz qemu-88d5814e6b02515f823086abb91dc7cdbb31c9f1.tar.bz2 |
Merge tag 'pull-nios2-20220426' of https://gitlab.com/rth7680/qemu into staging
Fix nios2-linux-user syscalls.
Fix nios2-linux-user sigreturn.
Enable tests for nios2-linux-user.
Remove special handling of SIGSEGV.
Check supervisor for eret, bret.
Split special registers out of env->regs[].
Clean up interrupt processing.
Raise unaligned data and destination exceptions.
Set TLBMISC fields correctly on exceptions.
Prevent writes to read-only or reserved control fields.
Use tcg_constant_tl().
Implement shadow register sets.
Implement external interrupt controller interface.
Implement vectored interrupt controller.
Enable semihosting tests for nios2-softmmu.
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* tag 'pull-nios2-20220426' of https://gitlab.com/rth7680/qemu: (68 commits)
tests/tcg/nios2: Add test-shadow-1
tests/tcg/nios2: Add semihosting multiarch tests
hw/nios2: Machine with a Vectored Interrupt Controller
hw/nios2: Move memory regions into Nios2Machine
hw/nios2: Introduce Nios2MachineState
hw/intc: Vectored Interrupt Controller (VIC)
linux-user/nios2: Handle various SIGILL exceptions
target/nios2: Advance pc when raising exceptions
target/nios2: Implement EIC interrupt processing
target/nios2: Update helper_eret for shadow registers
target/nios2: Implement rdprs, wrprs
target/nios2: Introduce shadow register sets
target/nios2: Implement Misaligned destination exception
target/nios2: Use tcg_gen_lookup_and_goto_ptr
target/nios2: Use gen_goto_tb for DISAS_TOO_MANY
target/nios2: Hoist set of is_jmp into gen_goto_tb
target/nios2: Create gen_jumpr
target/nios2: Enable unaligned traps for system mode
target/nios2: Drop CR_STATUS_EH from tb->flags
target/nios2: Introduce dest_gpr
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/intc/nios2_vic.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/include/hw/intc/nios2_vic.h b/include/hw/intc/nios2_vic.h new file mode 100644 index 0000000..af1517a --- /dev/null +++ b/include/hw/intc/nios2_vic.h @@ -0,0 +1,64 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel® Quartus® Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_INTC_NIOS2_VIC +#define HW_INTC_NIOS2_VIC + +#define TYPE_NIOS2_VIC "nios2-vic" +OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC) + +#define NIOS2_VIC_MAX_IRQ 32 + +struct Nios2VIC { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq output_int; + + /* properties */ + CPUState *cpu; + MemoryRegion csr; + + uint32_t int_config[NIOS2_VIC_MAX_IRQ]; + uint32_t vic_config; + uint32_t int_raw_status; + uint32_t int_enable; + uint32_t sw_int; + uint32_t vic_status; + uint32_t vec_tbl_base; + uint32_t vec_tbl_addr; +}; + +#endif /* HW_INTC_NIOS2_VIC */ |