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author | Peter Maydell <peter.maydell@linaro.org> | 2015-08-25 16:24:06 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2015-08-25 16:24:06 +0100 |
commit | 7df9671989c1cfa693764f9ae6349324b2ada02a (patch) | |
tree | 10cfbe17f8fc7f347abac4299f4834ae045a029e /include | |
parent | 34a4450434f1a5daee06fca223afcbb9c8f1ee24 (diff) | |
parent | cea66e91212164e02ad1d245c2371f7e8eb59e7f (diff) | |
download | qemu-7df9671989c1cfa693764f9ae6349324b2ada02a.zip qemu-7df9671989c1cfa693764f9ae6349324b2ada02a.tar.gz qemu-7df9671989c1cfa693764f9ae6349324b2ada02a.tar.bz2 |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150825-1' into staging
target-arm queue:
* add missing EL2/EL3 TLBI operations
* add missing EL2/EL3 ATS operations
* add missing EL2/EL3 registers
* update Xilinx MAINTAINERS info
* Xilinx: connect the four OCM banks
# gpg: Signature made Tue 25 Aug 2015 16:22:43 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
* remotes/pmaydell/tags/pull-target-arm-20150825-1:
target-arm: Implement AArch64 TLBI operations on IPAs
target-arm: Implement missing EL3 TLB invalidate operations
target-arm: Implement missing EL2 TLBI operations
target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch
target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
cputlb: Add functions for flushing TLB for a single MMU index
target-arm: Implement AArch32 ATS1H* operations
target-arm: Enable the AArch32 ATS12NSO ops
target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3
target-arm: Wire up AArch64 EL2 and EL3 address translation ops
target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations
target-arm: Implement missing ACTLR registers
target-arm: Implement missing AFSR registers
target-arm: Implement missing AMAIR registers
target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers
MAINTAINERS: Add ZynqMP to MAINTAINERS file
MAINTAINERS: Update Xilinx Maintainership
xlnx-zynqmp: Connect the four OCM banks
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/exec/exec-all.h | 47 | ||||
-rw-r--r-- | include/hw/arm/xlnx-zynqmp.h | 6 |
2 files changed, 53 insertions, 0 deletions
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 29775c0..fbc6dcb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -96,8 +96,46 @@ bool qemu_in_vcpu_thread(void); void cpu_reload_memory_map(CPUState *cpu); void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); /* cputlb.c */ +/** + * tlb_flush_page: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ void tlb_flush_page(CPUState *cpu, target_ulong addr); +/** + * tlb_flush: + * @cpu: CPU whose TLB should be flushed + * @flush_global: ignored + * + * Flush the entire TLB for the specified CPU. + * The flush_global flag is in theory an indicator of whether the whole + * TLB should be flushed, or only those entries not marked global. + * In practice QEMU does not implement any global/not global flag for + * TLB entries, and the argument is ignored. + */ void tlb_flush(CPUState *cpu, int flush_global); +/** + * tlb_flush_page_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @...: list of MMU indexes to flush, terminated by a negative value + * + * Flush one page from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...); +/** + * tlb_flush_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @...: list of MMU indexes to flush, terminated by a negative value + * + * Flush all entries from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx(CPUState *cpu, ...); void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); @@ -115,6 +153,15 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) static inline void tlb_flush(CPUState *cpu, int flush_global) { } + +static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, + target_ulong addr, ...) +{ +} + +static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) +{ +} #endif #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c379632..6ccb57b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -32,6 +32,10 @@ #define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_NUM_UARTS 2 +#define XLNX_ZYNQMP_NUM_OCM_BANKS 4 +#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 +#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 + #define XLNX_ZYNQMP_GIC_REGIONS 2 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets @@ -52,6 +56,8 @@ typedef struct XlnxZynqMPState { ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; + MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; + CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; |