Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.1

 * Improve device tree generation
 * Support configuarable marchid, mvendorid, mipid CSR values
 * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions
 * Fix incorrect PTE merge in walk_pte
 * Add TPM support to the virt board

# -----BEGIN PGP SIGNATURE-----
#
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# cFRLjgf9GFmxPhOC8cb7wN6xsiJIiVmmcTGHKfUgFTAIR2KLOEm2fo28YNrgewok
# Hi7FBHLhYKEivz70GFVg7q6oJlqhYx8fL4AB0sodTetIcJGQPQgz8zN7ZD8utnzA
# d6n7ZruyW5IuUqCBUcsHNqBHxoYanR88rr6YpxU+nSz0WALYRgQliXm5zqK1rwNc
# v8HpLHyN7JUmAQmJ1U6Uc6IFi/cFn9e/Hs/uRMevKov2nCTxeeAq5G2r8JGKpx35
# VRid91dcWbGiRY1xHWqnl/0WZxl8Jp4av1e5NDbXfwYPvwiI2fza5KFasp2S38yR
# VvnUcI+p73qclCF7LkfL9c//xQT1iA==
# =Xkoz
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 28 Apr 2022 09:30:29 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu: (25 commits)
  hw/riscv: Enable TPM backends
  hw/riscv: virt: Add device plug support
  hw/riscv: virt: Add support for generating platform FDT entries
  hw/riscv: virt: Create a platform bus
  hw/core: Move the ARM sysbus-fdt to core
  hw/riscv: virt: Add a machine done notifier
  target/riscv: add scalar crypto related extenstion strings to isa_string
  target/riscv: Fix incorrect PTE merge in walk_pte
  target/riscv: rvk: expose zbk* and zk* properties
  disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
  target/riscv: rvk: add CSR support for Zkr
  target/riscv: rvk: add support for zksed/zksh extension
  target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
  target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
  target/riscv: rvk: add support for sha256 related instructions in zknh extension
  target/riscv: rvk: add support for zkne/zknd extension in RV64
  target/riscv: rvk: add support for zknd/zkne extension in RV32
  crypto: move sm4_sbox from target/arm
  target/riscv: rvk: add support for zbkx extension
  target/riscv: rvk: add support for zbkc extension
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

3 files changed, 13 insertions, 1 deletions

diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index 0000000..9bd3ebc
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -0,0 +1,6 @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/include/hw/arm/sysbus-fdt.h b/include/hw/core/sysbus-fdt.h
index 340c382..340c382 100644
--- a/include/hw/arm/sysbus-fdt.h
+++ b/include/hw/core/sysbus-fdt.h
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 78b058e..984e55c 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,6 +45,8 @@ struct RISCVVirtState {
     MachineState parent;
 
     /*< public >*/
+    Notifier machine_done;
+    DeviceState *platform_bus_dev;
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *irqchip[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
@@ -75,6 +77,7 @@ enum {
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
     VIRT_PCIE_PIO,
+    VIRT_PLATFORM_BUS,
     VIRT_PCIE_ECAM
 };
 
@@ -84,9 +87,12 @@ enum {
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
     PCIE_IRQ = 0x20, /* 32 to 35 */
-    VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
+    VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
+    VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
 };
 
+#define VIRT_PLATFORM_BUS_NUM_IRQS 32
+
 #define VIRT_IRQCHIP_IPI_MSI 1
 #define VIRT_IRQCHIP_NUM_MSIS 255
 #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV