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author | Peter Maydell <peter.maydell@linaro.org> | 2020-11-19 21:56:15 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-12-10 11:44:56 +0000 |
commit | 6ba430b58abfdbe03cbdbad6188c7d0384fffbea (patch) | |
tree | 370f166b406bf7c730369eccc2a04dfdab97ce7f /include | |
parent | 46f4976f22a4549322307b34272e053d38653243 (diff) | |
download | qemu-6ba430b58abfdbe03cbdbad6188c7d0384fffbea.zip qemu-6ba430b58abfdbe03cbdbad6188c7d0384fffbea.tar.gz qemu-6ba430b58abfdbe03cbdbad6188c7d0384fffbea.tar.bz2 |
hw/intc/armv7m_nvic: Implement read/write for RAS register block
The RAS feature has a block of memory-mapped registers at offset
0x5000 within the PPB. For a "minimal RAS" implementation we provide
no error records and so the only registers that exist in the block
are ERRIIDR and ERRDEVID.
The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour
of the "nvic-default" region is actually valid for minimal-RAS,
so the main benefit of providing an explicit implementation of
the register block is more accurate LOG_UNIMP messages, and a
framework for where we could add a real RAS implementation later
if necessary.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/intc/armv7m_nvic.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 33b6d88..39c71e1 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,6 +83,7 @@ struct NVICState { MemoryRegion sysreg_ns_mem; MemoryRegion systickmem; MemoryRegion systick_ns_mem; + MemoryRegion ras_mem; MemoryRegion container; MemoryRegion defaultmem; |