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| author | Frederic Konrad <konrad.frederic@yahoo.fr> | 2025-05-26 10:55:21 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-06-16 11:26:25 +0100 |
| commit | 6559e7ad8e535b70e34c79076e6cb6c09d626d0d (patch) | |
| tree | 6f3bc1ab02dea1084130fb386fba3c4996933cf2 /include | |
| parent | 5dc8e4e892ba10e040d12afece0d36b8b6a269d6 (diff) | |
| download | qemu-6559e7ad8e535b70e34c79076e6cb6c09d626d0d.zip qemu-6559e7ad8e535b70e34c79076e6cb6c09d626d0d.tar.gz qemu-6559e7ad8e535b70e34c79076e6cb6c09d626d0d.tar.bz2 | |
hw/intc/arm_gic: introduce a first-cpu-index property
This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).
Signed-off-by: Clément Chigot <chigot@adacore.com>
Message-id: 20250526085523.809003-3-chigot@adacore.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: slightly expanded comment documenting GIC property]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/intc/arm_gic.h | 3 | ||||
| -rw-r--r-- | include/hw/intc/arm_gic_common.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 48f6a51..be923f7 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -27,6 +27,9 @@ * implement the security extensions * + QOM property "has-virtualization-extensions": set true if the GIC should * implement the virtualization extensions + * + QOM property "first-cpu-index": index of the first cpu attached to the + * GIC (default 0). The CPUs connected to the GIC are assumed to be + * first-cpu-index, first-cpu-index + 1, ... first-cpu-index + num-cpu - 1. * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32) * [0..P-1] SPIs * [P..P+31] PPIs for CPU 0 diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 97fea41..93a3cc2 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -129,6 +129,8 @@ struct GICState { uint32_t num_lrs; uint32_t num_cpu; + /* cpu_index of the first CPU, attached to this GIC. */ + uint32_t first_cpu_index; MemoryRegion iomem; /* Distributor */ /* This is just so we can have an opaque pointer which identifies |