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| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2023-06-16 09:38:03 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-10-01 13:55:38 +0100 |
| commit | 604b72dd3c393bf6a7cac59c3a74a2bec4673a80 (patch) | |
| tree | f5305421e1226dd793379126c63a66609ff77109 /include | |
| parent | e569d959336004be8e50547be381886ba8a6e3d0 (diff) | |
| download | qemu-604b72dd3c393bf6a7cac59c3a74a2bec4673a80.zip qemu-604b72dd3c393bf6a7cac59c3a74a2bec4673a80.tar.gz qemu-604b72dd3c393bf6a7cac59c3a74a2bec4673a80.tar.bz2 | |
hw/arm/xlnx: Connect secondary CGEM IRQs
The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
platforms have two priority queues with separate interrupt sources for
each. If the interrupt source for the second priority queue is not
connected, they work in polling mode only. This change connects the
second interrupt source for platforms where it is available. This patch
has been tested using the lwIP stack with a Xilinx-supplied driver from
their embeddedsw repository.
Signed-off-by: Kinsey Moore <kinsey.moore@oarcorp.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/xlnx-versal.h | 1 | ||||
| -rw-r--r-- | include/hw/arm/xlnx-zynqmp.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 025beb5..05ed641 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -78,6 +78,7 @@ struct Versal { struct { PL011State uart[XLNX_VERSAL_NR_UARTS]; CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; + OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; VersalUsb2 usb; CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 48f7948..c137ac5 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -116,6 +116,7 @@ struct XlnxZynqMPState { MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; + OrIRQState gem_irq_orgate[XLNX_ZYNQMP_NUM_GEMS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; SysbusAHCIState sata; |