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| author | Minwoo Im <minwoo.im@samsung.com> | 2024-05-28 11:31:06 +0900 |
|---|---|---|
| committer | Jeuk Kim <jeuk20.kim@samsung.com> | 2024-06-03 16:20:42 +0900 |
| commit | 5c079578d2e46df626d13eeb629c7d761a5c4e44 (patch) | |
| tree | 1e2dcd5a19216a0d8829843660de126fed02d259 /include | |
| parent | cdba3b901ac0b480eb9d940219113f0be80cc4e1 (diff) | |
| download | qemu-5c079578d2e46df626d13eeb629c7d761a5c4e44.zip qemu-5c079578d2e46df626d13eeb629c7d761a5c4e44.tar.gz qemu-5c079578d2e46df626d13eeb629c7d761a5c4e44.tar.bz2 | |
hw/ufs: Add support MCQ of UFSHCI 4.0
This patch adds support for MCQ defined in UFSHCI 4.0. This patch
utilized the legacy I/O codes as much as possible to support MCQ.
MCQ operation & runtime register is placed at 0x1000 offset of UFSHCI
register statically with no spare space among four registers (48B):
UfsMcqSqReg, UfsMcqSqIntReg, UfsMcqCqReg, UfsMcqCqIntReg
The maxinum number of queue is 32 as per spec, and the default
MAC(Multiple Active Commands) are 32 in the device.
Example:
-device ufs,serial=foo,id=ufs0,mcq=true,mcq-maxq=8
Signed-off-by: Minwoo Im <minwoo.im@samsung.com>
Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com>
Message-Id: <20240528023106.856777-3-minwoo.im@samsung.com>
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/block/ufs.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/include/block/ufs.h b/include/block/ufs.h index 3513b6e..92da7a8 100644 --- a/include/block/ufs.h +++ b/include/block/ufs.h @@ -152,7 +152,8 @@ REG32(MCQCONFIG, offsetof(UfsReg, mcqconfig)) FIELD(MCQCONFIG, MAC, 8, 8) #define UFS_INTR_MASK \ - ((1 << R_IS_CEFES_SHIFT) | (1 << R_IS_SBFES_SHIFT) | \ + ((1 << R_IS_CQES_SHIFT) | \ + (1 << R_IS_CEFES_SHIFT) | (1 << R_IS_SBFES_SHIFT) | \ (1 << R_IS_HCFES_SHIFT) | (1 << R_IS_UTPES_SHIFT) | \ (1 << R_IS_DFES_SHIFT) | (1 << R_IS_UCCS_SHIFT) | \ (1 << R_IS_UTMRCS_SHIFT) | (1 << R_IS_ULSS_SHIFT) | \ @@ -242,6 +243,21 @@ typedef struct QEMU_PACKED UfsMcqCqIntReg { REG32(CQIS, offsetof(UfsMcqCqIntReg, is)) FIELD(CQIS, TEPS, 0, 1) +/* + * Provide MCQ Operation & Runtime Registers as a contiguous addressed + * registers for the simplicity. + * DAO(Doorbell Address Offset) and ISAO(Interrupt Status Register Address + * Offset) registers should be properly configured with the following + * structure. + */ +#define UFS_MCQ_OPR_START 0x1000 +typedef struct QEMU_PACKED UfsMcqOpReg { + UfsMcqSqReg sq; + UfsMcqSqIntReg sq_int; + UfsMcqCqReg cq; + UfsMcqCqIntReg cq_int; +} UfsMcqOpReg; + typedef struct QEMU_PACKED DeviceDescriptor { uint8_t length; uint8_t descriptor_idn; @@ -1169,6 +1185,11 @@ static inline void _ufs_check_size(void) { QEMU_BUILD_BUG_ON(sizeof(UfsReg) != 0x38C); QEMU_BUILD_BUG_ON(sizeof(UfsMcqReg) != 64); + QEMU_BUILD_BUG_ON(sizeof(UfsMcqSqReg) != 20); + QEMU_BUILD_BUG_ON(sizeof(UfsMcqCqReg) != 8); + QEMU_BUILD_BUG_ON(sizeof(UfsMcqSqIntReg) != 8); + QEMU_BUILD_BUG_ON(sizeof(UfsMcqCqIntReg) != 12); + QEMU_BUILD_BUG_ON(sizeof(UfsMcqOpReg) != 48); QEMU_BUILD_BUG_ON(sizeof(DeviceDescriptor) != 89); QEMU_BUILD_BUG_ON(sizeof(GeometryDescriptor) != 87); QEMU_BUILD_BUG_ON(sizeof(UnitDescriptor) != 45); |