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| author | Glenn Miles <milesg@linux.ibm.com> | 2025-05-12 13:10:31 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-21 08:03:52 +0200 |
| commit | 555e446019f58e488ccf9fc416667be450e3f32f (patch) | |
| tree | 28e1bf079a974fabeab8b18e69c5accacd53d4d3 /include | |
| parent | b22ffb42999504614a1bef3a52c5b2e6549e8de6 (diff) | |
| download | qemu-555e446019f58e488ccf9fc416667be450e3f32f.zip qemu-555e446019f58e488ccf9fc416667be450e3f32f.tar.gz qemu-555e446019f58e488ccf9fc416667be450e3f32f.tar.bz2 | |
ppc/xive2: Support redistribution of group interrupts
When an XIVE context is pulled while it has an active, unacknowledged
group interrupt, XIVE will check to see if a context on another thread
can handle the interrupt and, if so, notify that context. If there
are no contexts that can handle the interrupt, then the interrupt is
added to a backlog and XIVE will attempt to escalate the interrupt,
if configured to do so, allowing the higher privileged handler to
activate a context that can handle the original interrupt.
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Michael Kowal <kowal@linux.ibm.com>
Tested-by: Gautam Menghani <gautam@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-23-npiggin@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/xive2_regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 2c535ec..e222038 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -224,6 +224,9 @@ typedef struct Xive2Nvgc { #define NVGC2_W0_VALID PPC_BIT32(0) #define NVGC2_W0_PGONEXT PPC_BITMASK32(26, 31) uint32_t w1; +#define NVGC2_W1_PSIZE PPC_BITMASK32(0, 1) +#define NVGC2_W1_END_BLK PPC_BITMASK32(4, 7) +#define NVGC2_W1_END_IDX PPC_BITMASK32(8, 31) uint32_t w2; uint32_t w3; uint32_t w4; |