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| author | Cédric Le Goater <clg@kaod.org> | 2019-11-25 07:58:13 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | 5373c61d6a7ec29c2b1126cb908fd08e23b4247b (patch) | |
| tree | 20f8190dc4baf346e717ad6a56b74061419c7392 /include | |
| parent | 74f23d433268a5b8020fc9d037d4512a55fe4d31 (diff) | |
| download | qemu-5373c61d6a7ec29c2b1126cb908fd08e23b4247b.zip qemu-5373c61d6a7ec29c2b1126cb908fd08e23b4247b.tar.gz qemu-5373c61d6a7ec29c2b1126cb908fd08e23b4247b.tar.bz2 | |
ppc/pnv: Clarify how the TIMA is accessed on a multichip system
The TIMA region gives access to the thread interrupt context registers
of a CPU. It is mapped at the same address on all chips and can be
accessed by any CPU of the system. To identify the chip from which the
access is being done, the PowerBUS uses a 'chip' field in the
load/store messages. QEMU does not model these messages, instead, we
extract the chip id from the CPU PIR and do a lookup at the machine
level to fetch the targeted interrupt controller.
Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
this process in pnv_xive_get_tctx(). The latter will be removed in the
subsequent patches but the same principle will be kept.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-14-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/pnv.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index a58cfea..3a7bc3c 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -103,6 +103,7 @@ typedef struct Pnv9Chip { * A SMT8 fused core is a pair of SMT4 cores. */ #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) typedef struct PnvChipClass { /*< private >*/ @@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) return pnv_chip_is_power9(pnv->chips[0]); } +PnvChip *pnv_get_chip(uint32_t chip_id); + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL |