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authorJulian Brown <julian@codesourcery.com>2017-02-07 18:29:59 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-07 18:29:59 +0000
commit40612000599e52e792d23c998377a0fa429c4036 (patch)
tree8549aae95f252fb42907a2e7678fed6fc6b4605e /include
parentf7478a92dd9ee2276bfaa5b7317140d3f9d6a53b (diff)
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arm: Correctly handle watchpoints for BE32 CPUs
In BE32 mode, sub-word size watchpoints can fail to trigger because the address of the access is adjusted in the opcode helpers before being compared with the watchpoint registers. This patch reverses the address adjustment before performing the comparison with the help of a new CPUClass hook. This version of the patch augments and tidies up comments a little. Signed-off-by: Julian Brown <julian@codesourcery.com> Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/qom/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index ca4d0fb..45bcf21 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -132,6 +132,8 @@ struct TranslationBlock;
* @cpu_exec_exit: Callback for cpu_exec cleanup.
* @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
* @disas_set_info: Setup architecture specific components of disassembly info
+ * @adjust_watchpoint_address: Perform a target-specific adjustment to an
+ * address before attempting to match it against watchpoints.
*
* Represents a CPU family or model.
*/
@@ -195,6 +197,7 @@ typedef struct CPUClass {
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
} CPUClass;
#ifdef HOST_WORDS_BIGENDIAN