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| author | Nicholas Piggin <npiggin@gmail.com> | 2025-05-12 13:10:49 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-07-21 08:03:53 +0200 |
| commit | 365e322cfb86b2e7131c3290c3a61f8d2bb224d3 (patch) | |
| tree | d0bbe9a618a370de2b098b0a139e33dbf6e39709 /include | |
| parent | 203181cebdb96283520b496d6eaa49634eb51579 (diff) | |
| download | qemu-365e322cfb86b2e7131c3290c3a61f8d2bb224d3.zip qemu-365e322cfb86b2e7131c3290c3a61f8d2bb224d3.tar.gz qemu-365e322cfb86b2e7131c3290c3a61f8d2bb224d3.tar.bz2 | |
ppc/xive2: implement NVP context save restore for POOL ring
In preparation to implement POOL context push, add support for POOL
NVP context save/restore.
The NVP p bit is defined in the spec as follows:
If TRUE, the CPPR of a Pool VP in the NVP is updated during store of
the context with the CPPR of the Hard context it was running under.
It's not clear whether non-pool VPs always or never get CPPR updated.
Before this patch, OS contexts always save CPPR, so we will assume that
is the behaviour.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Michael Kowal <kowal@linux.ibm.com>
Tested-by: Gautam Menghani <gautam@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-41-npiggin@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/xive2_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index f820546..2a3e60a 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -158,6 +158,7 @@ typedef struct Xive2Nvp { #define NVP2_W0_L PPC_BIT32(8) #define NVP2_W0_G PPC_BIT32(9) #define NVP2_W0_T PPC_BIT32(10) +#define NVP2_W0_P PPC_BIT32(11) #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */ #define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31) uint32_t w1; |