diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 14:55:43 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-01 14:55:43 +0000 |
| commit | 2357bca5328e9f6b1e0f14a3ac62a7f8b1aef557 (patch) | |
| tree | dbe5f92de22624f50849b84d5b78cdd0043e80b3 /include | |
| parent | e0b00f1b92d700171cfe39fac39de9fa75c1aecd (diff) | |
| download | qemu-2357bca5328e9f6b1e0f14a3ac62a7f8b1aef557.zip qemu-2357bca5328e9f6b1e0f14a3ac62a7f8b1aef557.tar.gz qemu-2357bca5328e9f6b1e0f14a3ac62a7f8b1aef557.tar.bz2 | |
hw/arm/armsse: Add unimplemented-device stub for cache control registers
The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/arm/armsse.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9855ec5..9d83005 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -150,6 +150,7 @@ typedef struct ARMSSE { UnimplementedDeviceState mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; + UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; /* * 'container' holds all devices seen by all CPUs. |