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| author | Cédric Le Goater <clg@kaod.org> | 2017-09-08 16:33:42 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-09-15 10:29:48 +1000 |
| commit | 21f3f8db0e61884ca48e9969b0305d54f1efe24b (patch) | |
| tree | 61ab79f0c997c318f802f004e6fd4bf6bfdf1b80 /include | |
| parent | 4c563d9df556454e6278035927e9e082a05b30af (diff) | |
| download | qemu-21f3f8db0e61884ca48e9969b0305d54f1efe24b.zip qemu-21f3f8db0e61884ca48e9969b0305d54f1efe24b.tar.gz qemu-21f3f8db0e61884ca48e9969b0305d54f1efe24b.tar.bz2 | |
ppc/xive: fix OV5_XIVE_EXPLOIT bits
On POWER9, the Client Architecture Support (CAS) negotiation process
determines whether the guest operates in XIVE Legacy compatibility or
in XIVE exploitation mode. Now that we have initial guest support for
the XIVE interrupt controller, let's fix the bits definition which have
evolved in the latest specs.
The platform advertises the XIVE Exploitation Mode support using the
property "ibm,arch-vec-5-platform-support-vec-5", byte 23 bits 0-1 :
- 0b00 XIVE legacy mode Only
- 0b01 XIVE exploitation mode Only
- 0b10 XIVE legacy or exploitation mode
The OS asks for XIVE Exploitation Mode support using the property
"ibm,architecture-vec-5", byte 23 bits 0-1:
- 0b00 XIVE legacy mode Only
- 0b01 XIVE exploitation mode Only
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/spapr_ovec.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index 9edfa5f..bf25e5d 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector; #define OV5_FORM1_AFFINITY OV_BIT(5, 0) #define OV5_HP_EVT OV_BIT(6, 5) #define OV5_HPT_RESIZE OV_BIT(6, 7) -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7) +#define OV5_XIVE_BOTH OV_BIT(23, 0) +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ /* ISA 3.00 MMU features: */ #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */ |