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authorPeter Maydell <peter.maydell@linaro.org>2019-02-28 10:55:16 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-28 11:03:04 +0000
commit0483641418643d5d4cc4d1328fe7acc4ab36c709 (patch)
tree369452b6cfc91601b9d403429845329156ea3515 /include
parent394e10d2bb300e4445b0ce37f6d138302f2ff04e (diff)
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hw/arm/iotkit-sysctl: Add SSE-200 registers
The SYSCTL block in the SSE-200 has some extra registers that are not present in the IoTKit version. Add these registers (as reads-as-written stubs), enabled by a new QOM property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219125808.25174-7-peter.maydell@linaro.org
Diffstat (limited to 'include')
-rw-r--r--include/hw/misc/iotkit-sysctl.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index 17a1455..9c2f23e 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -17,6 +17,9 @@
* "system control register" blocks.
*
* QEMU interface:
+ * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
+ * system information block of the SSE
+ * (used to identify whether to provide SSE-200-only registers)
* + sysbus MMIO region 0: the system information register bank
* + sysbus MMIO region 1: the system control register bank
*/
@@ -44,6 +47,23 @@ typedef struct IoTKitSysCtl {
uint32_t initsvtor0;
uint32_t cpuwait;
uint32_t wicctrl;
+ uint32_t scsecctrl;
+ uint32_t fclk_div;
+ uint32_t sysclk_div;
+ uint32_t clock_force;
+ uint32_t initsvtor1;
+ uint32_t nmi_enable;
+ uint32_t ewctrl;
+ uint32_t pdcm_pd_sys_sense;
+ uint32_t pdcm_pd_sram0_sense;
+ uint32_t pdcm_pd_sram1_sense;
+ uint32_t pdcm_pd_sram2_sense;
+ uint32_t pdcm_pd_sram3_sense;
+
+ /* Properties */
+ uint32_t sys_version;
+
+ bool is_sse200;
} IoTKitSysCtl;
#endif