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authorPeter Maydell <peter.maydell@linaro.org>2021-08-12 10:33:51 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-09-01 11:08:20 +0100
commit3b76e18520330e2a23c86d7c627c1cd4a3ed32f2 (patch)
treebdab5e9a7671c5496f0c2e67eb5dc4dfaed0c518 /include
parent9bfaf3754b71b72296f24f73876da67cf43c3e10 (diff)
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hw/arm/msf2-soc: Wire up refclk
Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a frequency which is programmably either /4, /8, /16 or /32 of the main CPU clock. We don't currently model the register which allows the guest to set the divisor, so implement the refclk as a fixed /32 of the CPU clock (which is the value of the divisor at reset). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-21-peter.maydell@linaro.org
Diffstat (limited to 'include')
-rw-r--r--include/hw/arm/msf2-soc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
index 01f904c..ce417a6 100644
--- a/include/hw/arm/msf2-soc.h
+++ b/include/hw/arm/msf2-soc.h
@@ -59,6 +59,7 @@ struct MSF2State {
uint64_t esram_size;
Clock *m3clk;
+ Clock *refclk;
uint8_t apb0div;
uint8_t apb1div;