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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-01-04 07:55:34 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-04 07:55:34 +0100 |
| commit | 6e8b990354d244ad5af40c747fdf3c008962b4e3 (patch) | |
| tree | 0e65c2d0e34eadbadf6ec696446caab29ba850be /include/qemu/buffer.h | |
| parent | 93130c8475692b1e52e3d3c3beedc3a79b4562d5 (diff) | |
| download | qemu-6e8b990354d244ad5af40c747fdf3c008962b4e3.zip qemu-6e8b990354d244ad5af40c747fdf3c008962b4e3.tar.gz qemu-6e8b990354d244ad5af40c747fdf3c008962b4e3.tar.bz2 | |
target/ppc: Cache per-pmc insn and cycle count settings
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[danielhb: fixed PMC4 cyc_cnt shift, insn run latch code,
MMCR0_FC handling, "PMC[1-6]" comment]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220103224746.167831-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/qemu/buffer.h')
0 files changed, 0 insertions, 0 deletions