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| author | Cédric Le Goater <clg@kaod.org> | 2019-11-25 07:58:14 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | d024a2c1114fadd9b0692be4e594a9b8b31197af (patch) | |
| tree | 403ef9158a85eb89c8e429a1199db2253864e4b1 /include/hw | |
| parent | 5373c61d6a7ec29c2b1126cb908fd08e23b4247b (diff) | |
| download | qemu-d024a2c1114fadd9b0692be4e594a9b8b31197af.zip qemu-d024a2c1114fadd9b0692be4e594a9b8b31197af.tar.gz qemu-d024a2c1114fadd9b0692be4e594a9b8b31197af.tar.bz2 | |
ppc/xive: Move the TIMA operations to the controller model
On the P9 Processor, the thread interrupt context registers of a CPU
can be accessed "directly" when by load/store from the CPU or
"indirectly" by the IC through an indirect TIMA page. This requires to
configure first the PC_TCTXT_INDIRx registers.
Today, we rely on the get_tctx() handler to deduce from the CPU PIR
the chip from which the TIMA access is being done. By handling the
TIMA memory ops under the interrupt controller model of each machine,
we can uniformize the TIMA direct and indirect ops under PowerNV. We
can also check that the CPUs have been enabled in the XIVE controller.
This prepares ground for the future versions of XIVE.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-15-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/ppc/xive.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 97bbcdd..dcf8974 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -462,7 +462,6 @@ typedef struct XiveENDSource { #define XIVE_TM_OS_PAGE 0x2 #define XIVE_TM_USER_PAGE 0x3 -extern const MemoryRegionOps xive_tm_ops; void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, |