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| author | Sunil V L <sunilvl@ventanamicro.com> | 2022-10-04 14:53:51 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-10-14 14:29:50 +1000 |
| commit | a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0 (patch) | |
| tree | 966c30581b5023a7f83f48d78bbf73ba0350e49d /include/hw | |
| parent | 90e26984eede1f4303572a39ee328f4c23b276a0 (diff) | |
| download | qemu-a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0.zip qemu-a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0.tar.gz qemu-a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0.tar.bz2 | |
hw/riscv: virt: Enable booting S-mode firmware from pflash
To boot S-mode firmware payload like EDK2 from persistent
flash storage, qemu needs to pass the flash address as the
next_addr in fw_dynamic_info to the opensbi.
When both -kernel and -pflash options are provided in command line,
the kernel (and initrd if -initrd) will be copied to fw_cfg table.
The S-mode FW will load the kernel/initrd from fw_cfg table.
If only pflash is given but not -kernel, then it is the job of
of the S-mode firmware to locate and load the kernel.
In either case, update the kernel_entry with the flash address
so that the opensbi can jump to the entry point of the S-mode
firmware.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221004092351.18209-4-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/riscv/boot.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index a36f761..93e5f87 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -57,5 +57,6 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, uint32_t reset_vec_size, uint64_t kernel_entry); void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr); +void riscv_setup_firmware_boot(MachineState *machine); #endif /* RISCV_BOOT_H */ |