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authorRichard Henderson <richard.henderson@linaro.org>2025-09-03 05:49:44 +0200
committerRichard Henderson <richard.henderson@linaro.org>2025-09-03 05:49:44 +0200
commita10631b0cf04ce7daf26648840df3f15bc36724e (patch)
tree72846208ab54e2f18510c72011e683fd3de9e66d /include/hw
parent8415b0619f65bff12f10c774659df92d3f61daca (diff)
parente502e614f4c3e5ee7b12cf1c926d9581262fd626 (diff)
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Merge tag 'hw-misc-20250902' of https://github.com/philmd/qemu into staging
Misc HW patches - Compile various system files once - Remove SDCard spec v1.10 - Remove mipssim machine and mipsnet device model - Prevent crash in e1000e when legacy interrupt fires after enabling MSI-X - Introduce qemu_init_irq_child() - Remove various memory leaks reported by ASan - Few Coverity fixes - Use 74Kf CPU to run MIPS16e binaries and M14Kc for microMIPS ones # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmi3FDYACgkQ4+MsLN6t # wN7fwA//WqegI1RTs65uHGV2M0vcYtGYTrucLyJtE9lJubb3wVjzdZpNcVVwKFRi # lXNjnOfmA7lIsC2CMRaiFO/hIk40yN2BLoEupSrLXjiygtiwlhG8OX0mU/6o06/k # Q41rEAu0wLVdJDpyUZWnVi1WvjMzaal3RvENRMr5CsrFw/Yk6Z7HKBDMEMuJjOWL # qBTAf8o8pnfliiyeS+OE4r5iIFUHzCtGlQtJH1GZ+zFgR2LNe6UUbofmUnzIFU0j # KuepdXemmd29nEz7wk8a7sjbJmoN9vLdJtsM+zcwNOsxmFC9+1ap/8BAGzRmhrWp # l5zJmL2YbvdHExKLC3qlnhGsKutK+9K4VAB6jLZu0MHfUQBYCGgFgYFcLdlGlRzg # OGgCvx5M7vZekTEHQu3zT29iUOAKAkD7dYlGIPqSUGuPGDZgPOqIMMc1HJAblXB1 # xNATGo2T2D3M01/ugwPAMF2IhLmKa9oAQDKnsW+bG6WJ4rjhqQpbmvxn51JB8q/x # a7xuUJa8BqX24NMo5d6JqPZPQhor0P0J0ws6oKutLf381FQ9JAnVEVmbQqPSijHY # BW3by77G2e97hfK0MwqUi43yuRHmNsh3flCdgCt7Zx6lsqmnMJuuhuOL4jQx6JRR # hPWDFiR+mns12AL3J56A0Y92enoLTawMzrA5M/06my9HLjXuu5M= # =WRLz # -----END PGP SIGNATURE----- # gpg: Signature made Tue 02 Sep 2025 05:58:46 PM CEST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250902' of https://github.com/philmd/qemu: (38 commits) hw/i386/pc_piix.c: remove unnecessary if() from pc_init1() hw/arm/boot: Correctly free the MemoryDeviceInfoList docs/about/removed-features: Clarify 'device_add' is removed hw/mips/malta: Include 'system/system.h' hw/mips/loongson3_virt: Include 'system/system.h' hw/isa/superio: Include 'system/system.h' hw/arm/virt: Include 'system/system.h' crypto/hmac: Allow to build hmac over multiple qcrypto_gnutls_hmac_bytes[v] calls hw/sd/sdcard: Refactor sd_bootpart_offset hw/sd/sdcard: Add validation for boot-partition-size hw/net: Remove mipsnet device model hw/mips: Remove mipssim machine hw/display/xlnx_dp: Don't leak dpcd and edid objects hw/misc/xlnx-versal-cframe-reg: Free FIFO, g_tree on deinit hw/char/max78000_uart: Destroy FIFO on deinit hw/gpio/pca9554: Avoid leak in pca9554_set_pin() hw/ide/ich.c: Use qemu_init_irq_child() to avoid memory leak hw/char/serial-pci-multi: Use qemu_init_irq_child() to avoid leak hw/irq: New qemu_init_irq_child() function hw/ppc: Fix build error with CONFIG_POWERNV disabled ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/irq.h23
-rw-r--r--include/hw/sd/sd.h1
-rw-r--r--include/hw/ssi/ssi.h14
3 files changed, 36 insertions, 2 deletions
diff --git a/include/hw/irq.h b/include/hw/irq.h
index b301223..291fdd6 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -36,12 +36,33 @@ static inline void qemu_irq_pulse(qemu_irq irq)
/*
* Init a single IRQ. The irq is assigned with a handler, an opaque data
- * and the interrupt number.
+ * and the interrupt number. The caller must free this with qemu_free_irq().
+ * If you are using this inside a device's init or realize method, then
+ * qemu_init_irq_child() is probably a better choice to avoid the need
+ * to manually clean up the IRQ.
*/
void qemu_init_irq(IRQState *irq, qemu_irq_handler handler, void *opaque,
int n);
/**
+ * qemu_init_irq_child: Initialize IRQ and make it a QOM child
+ * @parent: QOM object which owns this IRQ
+ * @propname: child property name
+ * @irq: pointer to IRQState to initialize
+ * @handler: handler function for incoming interrupts
+ * @opaque: opaque data to pass to @handler
+ * @n: interrupt number to pass to @handler
+ *
+ * Init a single IRQ and make the IRQ object a child of @parent with
+ * the child-property name @propname. The IRQ object will thus be
+ * automatically freed when @parent is destroyed.
+ */
+void qemu_init_irq_child(Object *parent, const char *propname,
+ IRQState *irq, qemu_irq_handler handler,
+ void *opaque, int n);
+
+
+/**
* qemu_init_irqs: Initialize an array of IRQs.
*
* @irq: Array of IRQs to initialize
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
index 55d363f..91b5c40 100644
--- a/include/hw/sd/sd.h
+++ b/include/hw/sd/sd.h
@@ -56,7 +56,6 @@
#define AKE_SEQ_ERROR (1 << 3)
enum SDPhySpecificationVersion {
- SD_PHY_SPECv1_10_VERS = 1,
SD_PHY_SPECv2_00_VERS = 2,
SD_PHY_SPECv3_01_VERS = 3,
};
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index 3cdcbd5..2ad8033 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -38,6 +38,7 @@ struct SSIPeripheralClass {
/* if you have standard or no CS behaviour, just override transfer.
* This is called when the device cs is active (true by default).
+ * See ssi_transfer().
*/
uint32_t (*transfer)(SSIPeripheral *dev, uint32_t val);
/* called when the CS line changes. Optional, devices only need to implement
@@ -52,6 +53,7 @@ struct SSIPeripheralClass {
* of the CS behaviour at the device level. transfer, set_cs, and
* cs_polarity are unused if this is overwritten. Transfer_raw will
* always be called for the device for every txrx access to the parent bus
+ * See ssi_transfer().
*/
uint32_t (*transfer_raw)(SSIPeripheral *dev, uint32_t val);
};
@@ -110,6 +112,18 @@ bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
/* Master interface. */
SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
+/**
+ * Transfer a word on a SSI bus
+ * @bus: SSI bus
+ * @val: word to transmit
+ *
+ * At the same time, read a word and write the @val one on the SSI bus.
+ *
+ * SSI words might vary between 8 and 32 bits. The same number of bits
+ * written is received.
+ *
+ * Return: word value received
+ */
uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
DeviceState *ssi_get_cs(SSIBus *bus, uint8_t cs_index);