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| author | Cédric Le Goater <clg@kaod.org> | 2019-07-01 17:26:17 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-07-01 17:28:59 +0100 |
| commit | 6da4433fc5fa8aff1096cc651c8d313c70ee6f4d (patch) | |
| tree | 0ffaad3157d8abb9216a61ca5996a5d95ac38bd7 /include/hw | |
| parent | ad1a9782186d0ed1c02eb008f268d34599a54a42 (diff) | |
| download | qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.zip qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.tar.gz qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.tar.bz2 | |
aspeed/smc: add a 'sdram_base' property
The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190618165311.27066-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/ssi/aspeed_smc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 3b1e7fc..591279b 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -97,6 +97,9 @@ typedef struct AspeedSMCState { uint8_t r_timings; uint8_t conf_enable_w0; + /* for DMA support */ + uint64_t sdram_base; + AspeedSMCFlash *flashes; uint8_t snoop_index; |