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| author | BALATON Zoltan <balaton@eik.bme.hu> | 2022-09-24 14:28:05 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-10-17 16:15:09 -0300 |
| commit | 5f7effe4df91702add08e3e3dc1871fd35a8903f (patch) | |
| tree | 89358baf72693eebfcda20b276612de1d74dfc94 /include/hw | |
| parent | ef10aebb9a71f0c60f0b7aae808498333bb7bfd9 (diff) | |
| download | qemu-5f7effe4df91702add08e3e3dc1871fd35a8903f.zip qemu-5f7effe4df91702add08e3e3dc1871fd35a8903f.tar.gz qemu-5f7effe4df91702add08e3e3dc1871fd35a8903f.tar.bz2 | |
ppc440_sdram: QOM'ify
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <3e82ae575c7c41e464a0082d55ecb4ebcc4d4329.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/ppc/ppc4xx.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index fd0b3ca..ff88385 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -37,8 +37,6 @@ typedef struct { uint32_t bcr; } Ppc4xxSdramBank; -void ppc4xx_sdram_ddr2_enable(CPUPPCState *env); - void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, Ppc4xxSdramBank ram_banks[], const ram_addr_t sdram_bank_sizes[]); @@ -138,4 +136,20 @@ struct Ppc4xxSdramDdrState { void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s); +/* SDRAM DDR2 controller */ +#define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2); +struct Ppc4xxSdramDdr2State { + Ppc4xxDcrDeviceState parent_obj; + + MemoryRegion *dram_mr; + uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */ + Ppc4xxSdramBank bank[4]; + + uint32_t addr; + uint32_t mcopt2; +}; + +void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s); + #endif /* PPC4XX_H */ |