diff options
| author | Andrew Jeffery <andrew@aj.id.au> | 2018-07-16 17:18:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-07-16 17:18:41 +0100 |
| commit | 333b9c8a684c58f6711521e446e4b26de5addadc (patch) | |
| tree | 58025693c3940e354eb86b3402c476422740f335 /include/hw | |
| parent | 628fc75f3a3bb115de3b445c1a18547c44613cfe (diff) | |
| download | qemu-333b9c8a684c58f6711521e446e4b26de5addadc.zip qemu-333b9c8a684c58f6711521e446e4b26de5addadc.tar.gz qemu-333b9c8a684c58f6711521e446e4b26de5addadc.tar.bz2 | |
aspeed: Implement write-1-{set, clear} for AST2500 strapping
The AST2500 SoC family changes the runtime behaviour of the hardware
strapping register (SCU70) to write-1-set/write-1-clear, with
write-1-clear implemented on the "read-only" SoC revision register
(SCU7C). For the the AST2400, the hardware strapping is
runtime-configured with read-modify-write semantics.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20180709143524.17480-1-andrew@aj.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/misc/aspeed_scu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index f662c38..38996ad 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -41,6 +41,8 @@ typedef struct AspeedSCUState { #define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A1_SILICON_REV 0x04010303U +#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) + extern bool is_supported_silicon_rev(uint32_t silicon_rev); #define ASPEED_SCU_PROT_KEY 0x1688A8A8 |