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| author | Joel Stanley <joel@jms.id.au> | 2019-07-01 17:26:18 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-07-01 17:29:00 +0100 |
| commit | 3059c2f5a813ea2af0761705abc18848cd4e3c85 (patch) | |
| tree | 25e1a6d582bf59a68dad83d34458e179cb74ebb0 /include/hw | |
| parent | ebd205c0807a146bf272208f3d41728d5e985ceb (diff) | |
| download | qemu-3059c2f5a813ea2af0761705abc18848cd4e3c85.zip qemu-3059c2f5a813ea2af0761705abc18848cd4e3c85.tar.gz qemu-3059c2f5a813ea2af0761705abc18848cd4e3c85.tar.bz2 | |
aspeed: Link SCU to the watchdog
The ast2500 uses the watchdog to reset the SDRAM controller. This
operation is usually performed by u-boot's memory training procedure,
and it is enabled by setting a bit in the SCU and then causing the
watchdog to expire. Therefore, we need the watchdog to be able to
access the SCU's register space.
This causes the watchdog to not perform a system reset when the bit is
set. In the future it could perform a reset of the SDMC model.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190621065242.32535-1-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/watchdog/wdt_aspeed.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index 88d8be4..daef0c0 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -27,6 +27,7 @@ typedef struct AspeedWDTState { MemoryRegion iomem; uint32_t regs[ASPEED_WDT_REGS_MAX]; + AspeedSCUState *scu; uint32_t pclk_freq; uint32_t silicon_rev; uint32_t ext_pulse_width_mask; |