diff options
| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:14 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6 (patch) | |
| tree | 2e1a7c7e45eff69893f38bc9cb7448385b5a21b9 /include/hw | |
| parent | 9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae (diff) | |
| download | qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.zip qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.tar.gz qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.tar.bz2 | |
hw/riscv: Move sifive_u_otp model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/misc/sifive_u_otp.h (renamed from include/hw/riscv/sifive_u_otp.h) | 0 | ||||
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
2 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h index 6392975..6392975 100644 --- a/include/hw/riscv/sifive_u_otp.h +++ b/include/hw/misc/sifive_u_otp.h diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index cbeb228..936a3bd 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -24,7 +24,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" -#include "hw/riscv/sifive_u_otp.h" +#include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" |