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author | Nicholas Piggin <npiggin@gmail.com> | 2024-05-24 21:58:18 +1000 |
---|---|---|
committer | Nicholas Piggin <npiggin@gmail.com> | 2024-07-26 09:21:06 +1000 |
commit | 0ca94b2f11223d41258e6a7a046e5ccde831de46 (patch) | |
tree | 11d1d73e720853b018ac7dbe0566246957f1488c /include/hw | |
parent | 060e61436794d13ede9a1d0eb2b1d0cf3b7cfcfd (diff) | |
download | qemu-0ca94b2f11223d41258e6a7a046e5ccde831de46.zip qemu-0ca94b2f11223d41258e6a7a046e5ccde831de46.tar.gz qemu-0ca94b2f11223d41258e6a7a046e5ccde831de46.tar.bz2 |
ppc/pnv: Move timebase state into PnvCore
The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed by the chiptod, which limits programming the timebase
side of the state machine to thread 0 of a core.
Move the state out into PnvCore and share it among all threads.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'include/hw')
-rw-r--r-- | include/hw/ppc/pnv_core.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 29cab9d..ffec851 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -25,6 +25,20 @@ #include "hw/ppc/pnv.h" #include "qom/object.h" +/* Per-core ChipTOD / TimeBase state */ +typedef struct PnvCoreTODState { + int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ + int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ + + /* + * "Timers" for async TBST events are simulated by mfTFAC because TFAC + * is polled for such events. These are just used to ensure firmware + * performs the polling at least a few times. + */ + int tb_state_timer; + int tb_sync_pulse_timer; +} PnvCoreTODState; + #define TYPE_PNV_CORE "powernv-cpu-core" OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass, PNV_CORE) @@ -38,6 +52,9 @@ struct PnvCore { uint32_t pir; uint32_t hwid; uint64_t hrmor; + + PnvCoreTODState tod_state; + PnvChip *chip; MemoryRegion xscom_regs; |